The present invention lies in the field of active power management (APM) which means the short term control of processor clock frequencies and core supply voltage (Vdd) to minimise power consumption in an active mode. Active power management is generally a fast power management component, where clock frequencies and voltages may need to be modified every few hundred microseconds. Decisions are based on short term application needs.
A number of active power management schemes exist. Many such schemes which are used to find the optimum Vdd/clock frequency match assume that both parameters can be changed in a continuous manner. Such power models are not applicable in an architecture where supply voltage and/or clock frequency have a defined granularity.
It is an aim of the present invention to provide a method and system for controlling the clock frequency of a processor which can alleviate the limitations which exist where a clock frequency can only be changed with granularity.